1. Technical Field
The present invention relates to a voltage shift control circuit intended to be placed in parallel with at least one voltage shift capacitor coupling the phase or frequency comparator and the voltage controlled oscillator of a phase locked loop (PLL).
2. Related Art
PLLs have numerous uses in the electronics industry, among which is the generation of phase modulated or frequency modulated signals. The applications of the present invention are particularly intended for this use. In fact the invention can be applied in particular to the radio-frequency (RF) transmitters of fixed stations and of mobile terminals of digital radio-communications systems.
FIG. 1 illustrates the operating principle of a PLL. The PLL comprises a phase or frequency comparator (PFD) 10 which receives two input signals. The first one is a phase or frequency reference signal FREF and the second one is a signal FVCO coming from a voltage controlled oscillator (VCO) 30 and having undergone a frequency division in a variable ratio frequency divider 40. The output voltage of the PFD is integrated by a low pass filter 20, called a loop filter. The output of the filter controls the VCO in such a way as to align the phases of the two input signals FREF and FVCO of the PFD. The VCO delivers the output signal of the PLL which oscillates about a reference frequency controlled and modulated by the PLL.
It is possible to introduce frequency modulation (FM) at the level of the divider 40 by controlling the variable division ratio.
The performance characteristics of the PLL determine, in particular, the spectral purity of the output signal and the linearity of the modulation. In this respect, the absence of noise on the input of the VCO and the linearity of the gain of the PFD are of great importance. Embodiments of the PFD have been proposed which favour the linearity of the gain (see WO 97/01884). These embodiments necessitate that the DC component of the output signal of the PFD should correspond with an operating point substantially corresponding to the common mode (CM) voltage, that is to say to Vdd/2, where Vdd denotes the power supply voltage of the PLL.
In order to be able to change channels in the transmitter incorporating the PLL, means are provided for changing the DC component at the input of the VCO. In fact, the mean frequency of the output signal varies according to the channel used, which means that the theoretical mean voltage at the input of the VCO can vary from 0 to Vdd. The means forming a voltage translator comprise, for example, a high value capacitor placed in series between the output of the PFD and the input of the VCO.
Fast charging (or discharging) of this capacitor is desirable in order to reduce the time lost when changing channels, in particular during handover operations of the mobile terminal comprising the PLL. Even though in the rest of this description reference is made only to the charging of the capacitor, it is of course understood that this term refers both to the capacitive charging and to the capacitive discharging of this component, the capacitive charging being obtained by a positive charging current and the capacitive discharging being obtained by a negative charging current.